Charge trapping memory cells, such as planar SONOS memory cells or NROM memory cells are discussed in U.S. Pat. Nos. 5,768,192 and 6,011,725 or International Publication No. WO 99/60631. These devices have an oxide-nitride-oxide storage layer sequence as gate dielectric and are programmed by channel hot electrons (CHE) and erased by hot holes. A virtual ground array comprising NROM cells is usually provided with word lines which run above the source/drain regions and cross with buried bit lines. The transistor current therefore flows parallel to the word lines. This results in various difficulties: the memory transistors cannot be optimized by a precise setting of the source/drain dopings. The word lines have a small cross section, so that fast access to the memory contents is not possible owing to the low electrical conductivity caused as a result of said small cross section.
U.S. Pat. No. 5,679,591 describes a method for fabricating a contactless semiconductor memory with bit lines on the top side, in which bit line strips are in each case arranged between the word line stacks and interconnect the source/drain regions of the successive memory transistors along the word lines. The channel regions are oriented transversely with respect to the word lines and are isolated from one another by trench isolations.